1. Field of the Invention
The present invention relates to digital phase locked loop control devices, and more specifically to an out-of-lock detector for use in conjunction with a phase detector in a digital phase locked loop.
2. Description of the Prior Art
Phase locked loops are well known in the prior art, and the digital phase locked loop basically includes a phase detector, a voltage controlled oscillator, and a frequency divider. The phase detector receives a stable reference frequency signal from an external source and an output signal from the voltage controlled oscillator. The phase detector continuously compares the phase of the stable reference frequency signal to the phase of the voltage controlled oscillator output signal whereby the output signal of the phase detector is a measure of the phase differences between the two input signals. If there is a phase difference, the phase detector causes an error voltage to be applied to the voltage controlled oscillator. The voltage controlled oscillator output signal varies in response to the error voltages until the frequency of the voltage controlled oscillator output signal is exactly equal to the average frequency of the stable reference frequency signal. Whenever the phase detector continuously compares two in phase input signals, i.e., the stable reference frequency signal and the voltage controlled oscillator output signal, the phase lock loop is said to be locked. If phase differences between the voltage controlled oscillator's output signal and the stable reference frequency signal reoccur at the phase detector, the phase locked loop is said to be in an out-of-lock condition, and the phase detector introduces new error voltages until the phase locked loop is once again locked.
It is, therefore, apparent that there is a need to determine when the digital phase locked loop is in an out-of-lock condition. Prior art out-of-lock detectors utilized voltage level sensors which measured the magnitude of the error between the stable reference frequency signal and the voltage controlled oscillator's output signal. When the error between these two signals fell below a predetermined value, there was an in-lock signal indication. These analog devices are inefficient due to their slowness which is caused by the necessity of waiting for the measured analog voltages to settle out. There are digital phase lock detectors that do not include analog voltage level sensors. These phase lock detectors are specifically designed for use with a digital frequency synthesizer, and it is not apparent that these digital phase lock detectors can be easily adapted for use with other phase locked loop designs. The digital frequency synthesizer phase lock detector broadens the range of tolerable phase error over the prior art analog devices, but these digital phase detectors still provide out-of-lock signals when there are insignificant single bit discrepancies, such as a noise pulse, in the signals processed by the phase locked loop.
Accordingly, there is a need for a fast digital phase locked loop out-of-lock detector that is adaptable for use with all typical applications of the digital phase locked loop. Furthermore, there is a need for a digital phase locked loop out-of-lock detector which will ignore signal single bit discrepancies in the signals processed by the digital phase locked loop, and thus effectively further broaden the range of tolerable phase error.